ERPCL All-Digital BPSK Demodulator
BPSK16K-1.7M pdf Datasheet

* Utilizes digital ASIC technology to implement an all-digital demodulator.

* Coherent demodulation of up to 16-kbps BPSK signals modulated onto a subcarrier up to 1.7-MHz. It is compatible with the NASA STDN and Air Force SGLS standards.

* Bi-phase-L and NRZ-L signaling formats.

* BER performance within 1.5-dB of theoretical over an Eb/No of 2- to 12-dB.

* Power dissipation < 5 W. Single 28-V supply.

* Frame synchronization algorithm implemented internally.

* Balanced outputs drive 75-W loads compatible with EIA Standards RS-485 and RS-422A.

* Operating temperature range from -20°C to +70°C.


* All digital parameters are reconfigurable on the fly via an RS232 interface.


The SMC DMBP1700M-16K utilizes state-of-the-art digital ASIC technology to implement an all digital subcarrier demodulator (SCDM), compatible with the NASA STDN and Air Force SGLS standards. The input to the unit is a 16-kbps BPSK signal modulating a 1.7-MHz carrier.

A 64-kHz bandpass filter limits the noise bandwidth at the front end, thus maximizing the Analog-to-Digital Converter (ADC) dynamic range. The digital components operate at an 8-MHz clock rate, well in excess of the Nyquist requirements. The digital downconverter translates the received digitized signal to baseband. The bit synchronizer provides a feedback signal to the digital downconverter for coherent carrier tracking. It also provides clock recovery and data alignment.

A TMS320C30 Digital Signal Processor (DSP) processes the recovered bit stream. This includes implementation of a frame-synchronization algorithm. It monitors the downconversion feedback process to determine when phase lock has occurred. Bit-synchronizer information is monitored to determine when bit synchronization has occurred. TTL diagnostic signals are provided for external monitoring of the entire acquisition process.

The raw baseband-data and bit-sync-data are provided as test outputs for monitoring BER performance in the NRZ-L mode.

Operational parameters and modes are programmed vias an RS-232 interface to an IBM-compatible PC. In the Bi-phase-L mode, clock ambiguity is resolved in the DSP, soft decision information is stored over both halves of the 32-kbps effective bit interval and summed for hard decision. This restores the BER performance to that of 16-kbps NRZ-L data.