All-Digital Transponder
STDN/SGLS Transponder Contact Rock Systems For More Information

This project, developed through an SBIR with NASA Johnson Space Center, was designed as a test bed to evaluate key issues associated with an all-digital receiver/transmitter. The front-end up and downconverters are still analog in nature, but all phase-locked tracking loops are implemented digitally. Hence, loop bandwidths, data rates, and frame synchronization characteristics may be changed by simply modifying constants in the digital hardware.

The transponder is designed to receive a signal from the ground (or shuttle), demodulate the signal to extract command and control information, and generate a return carrier signal that contains either ranging or telemetry data to be transmitted back to the ground.

The STDN waveform comprises a BPSK-subcarrier signal phase modulated onto an S-Band carrier. The transponder must phase lock to the transmitted signal, determine its frequency and generate a return carrier that is exactly 240/221 times the received signal. An analog downconverter is used to translate the S-Band received signal to an intermediate frequency (IF) of ~3 MHz in a non-coherent mode. An all-digital carrier tracking loop is used to coherently extract the carrier from the received IF signal. Once the carrier has been extracted, the subcarrier must be demodulated to extract baseband data. The subcarrier lock and bit-synchronization are performed using an all-digital early-late integrate-and-dump (I&D) technique. The transponder design also incorporates the option to perform frame synchronization and Viterbi decoding if desired.

A flexible RF front-end supports selection of any of the STDN channels. The receiver downconverts the S-Band incoming signal to the 3-MHz IF for I- and Q-detection. The outgoing signal is translated from the IF to S-Band via a triple conversion process that maintains the coherent Rx to Tx relationship. An S-Band linear phase modulator supports direct modulation of the outgoing carrier signal.

The heart of the system is the all-digital receiver. An Altera 10K100 field-programmable gate array (FPGA) is used to implement a carrier-tracking algorithm developed at the Jet Propulsion Laboratory (JPL) that supports 1st-, 2nd-, or 3rd-order phase-locked loop (PLL) operation by simply changing the digital loop filter coefficients. Two commercially available application specific integrated circuits (ASICs) are used to implement the subcarrier and bit-synchronization sections. A Texas Instruments TMS320C31 digital signal processor (DSP) is used for frame synchronization, system control, and communications interface to an IBM-compatible PC. Every system variable is editable via the RS-232 interface to the PC.

One of the main features of the design is its ability to acquire the received signal with modulation applied. This prevents having to perform a tedious acquisition exercise to lock the two links prior to transmitting data. Further, if lock is lost temporarily the system reacquires automatically. This is accomplished by sampling the incoming waveform, transforming the time data to the frequency domain, and looking for the STDN characteristic waveform signature. The system provides the capability to detect if the carrier tracking loop is locked to a sideband and can automatically correct the target local oscillators to cause the system to lock to the correct signal.

System diagnostic data is available for download. A Visual Basic (VB) interface program was developed that provides the capability to program all variables, capture diagnostic information, display graphical data, calculate loop-filter constants, etc.. The diagnostic information provides insight into system operation. For example, the loop-filter phase error vs. time is useful for observing how the carrier-tracking loop reacts to various signal dynamics, such as Doppler, acceleration, or jerk.

Finally, two test boxes were designed to prove functionality. The first box allows the operator to create a signal with a defined signal-to-noise ratio (SNR) at the final IF frequency. A broadband white-noise generator followed by a variable attenuator is combined with an injected signal to create the desired SNR.

A second test box was developed to generate the STDN waveform and characterize the return. It supports data rates up to 16?kbps; may be used to insert a unique word into the data stream, thus avoiding BPSK phase ambiguity problems; can insert predefined errors into the unique word to test Hamming performance; and has built-in error rate counters. The companion VB program supports reading of data to calculate bit error rate (BER). Frame length, frame word, data rate, and subcarrier frequency are all selectable via dip switch settings. Additionally, the box provides BNC connectors and LED lights that indicate system state.